CUDA++ · open source, MIT
It runs on the NVIDIA GPUs people already own, with no NVIDIA user-space software: no CUDA toolkit, no nvcc, no PTX, no libcuda, no cuBLAS. It is its own open source project, under the MIT licence, in the repository aien-dev/CUDAplusplus.
It runs on the NVIDIA GB10 in the DGX Spark today. On 2026-10-21 the 35 billion parameter model AIEN serves on the Spark was running on this code with zero CUDA libraries loaded.
What it is for
Less computation, out of the big data centers.
The goal is not a faster way to rent a data center. It is to need less of one: the same work with fewer bytes moved, fewer operations and fewer joules per answer, so it runs on a machine a person owns (a DGX Spark, a PC with one graphics card, a laptop). Every result is reported as work per answer, against the machine's own ceiling.
Omega docs/OMEGA.mdThe repository
The repository is private until its licence and safety audit is done (ledger L395), then it is made public. Until then the links into it on this page do not open.
The audit, docs/AUDIT.mdWritten from the CUDA++ README (main at fc90713), docs/HOW_WE_DID_IT.md (branch docs/how-we-did-it at 62ea5a2) and Omega's docs/OMEGA.md (branch docs/what-omega-is at 89aad7c), checked 2026-10-22. Ledger item L402 tracks this page; L395 owns the repository. Work that is not done shows as in progress with its ledger id. The rest of Omega: What Omega is. Data file: /cudaplusplus.json.
1 · From your program to the chip
Each step a GPU program goes through, top to bottom, with the NVIDIA part CUDA uses there and what CUDA++ uses instead. The line on the left is lit by whose code runs: green ours with a receipt, blue ours in part, amber ours being built, grey NVIDIA's. Today 3 steps are ours with a receipt and 1 is being built.
Write a kernel
CUDA CUDA C++
CUDA++ The kernel builder, called from C. Omega's own languages reaching the GPU is Omega bar C1, built on this toolchain.
Compile to machine code
CUDA nvcc, NVVM, PTX, ptxas
CUDA++ Our own sm_121 encoder and register allocator: 59 instruction kinds, launch descriptors.
Talk to the driver
CUDA libcuda
CUDA++ Our own client for the open kernel module's ioctls, written from its MIT headers.
Run work
CUDA libcudart
CUDA++ Session, command lists and job engine: device, memory, upload, launch.
Libraries
CUDA cuBLAS, cuDNN, CUB
CUDA++ Matrix multiply (BF16, FP8, 4 bit, ternary), decode and prefill attention, frozen-order reductions.
Feed the math cores
CUDA nothing: left to you
CUDA++ The motor, the ++ in CUDA++: one schedule built before anything runs, movement engines that check every weight part, and the stroke, many conversations on one read of the weights.
Kernel driver
CUDA nvidia.ko, nvidia-uvm.ko
CUDA++ AIEN's own GB10 driver. Its simulator gates pass; it has not run on the chip yet.
Inside the GPU
CUDA GSP firmware
CUDA++ Stays NVIDIA's. The chip checks the firmware's signature and boots nothing else. CUDA++ never ships it.
2 · How we did it
One person and a team of AI coding agents, one DGX Spark, four weeks. NVIDIA publishes the source of its Linux kernel module, but not its compiler, its driver library or the GPU's machine code. So we skipped every closed layer.
libcuda is closed, but everything it does to the hardware goes through ioctls that the open kernel module defines in its public headers. We copied 67 of those headers unchanged (MIT) and wrote our own client against them: client, device, address space, memory, command ring, compute object, doorbell, completion.
Source on GitHubNVIDIA does not publish the GPU's instruction encoding. We compiled small probe kernels of our own once with NVIDIA's compiler, read the machine code back with NVIDIA's disassembler as an offline oracle, and compared kernels that differ in one detail to see which bits mean what. We cross-checked against Mesa's open NVIDIA compiler, NAK, and believed nothing until the chip ran it and gave the right answer. The tensor-core arithmetic was measured on the chip over 2,048 cases until one model matched every output bit.
Source on GitHubA launch on Blackwell is a short list of commands in the channel ring. We took their order from Mesa's NVK Vulkan driver and the method offsets from the open headers, built our own command lists, and measured them: about 24 to 31 microseconds per extra dependent launch.
Source on GitHub2026-09-26 vector add on the GB10. 2026-10-02 numerics closed on the chip. 2026-10-13 our own probes measured the tensor cores at 115.14 TFLOPS and memory reads at 195.1 GB/s. 2026-10-21 a 35B model served on this code with zero CUDA libraries in the process.
Source on GitHub3 · CUDA's pain points
What makes CUDA hard to use and hard to leave, how CUDA++ fixes each one, and the command that shows it. A row is marked fixed only with its receipt.
Being written in docs/PAIN_POINTS.md and a README section of CUDA++: each pain point people report, how CUDA++ answers it, and the one command that shows the answer.
Source on GitHub4 · Swap CUDA out
Take CUDA off a machine and put CUDA++ in its place, all the way down to the kernel driver, with one command each way.
A drop-in libcuda.so.1 on the CUDA++ runtime, so a CUDA program runs unmodified on CUDA++. One command in, one command back. Written up in docs/SWAP.md.
Source on GitHubPackaging, switch and rollback that replace nvidia.ko and nvidia-uvm.ko with AIEN's own GB10 driver. L401 builds the packaging; L332 builds the driver, whose simulator gates pass and which has not run on the chip yet.
Source on GitHub